preface
1 introduttion
1.1 modern digital design
1.2 cmos technology
1.3 programmable logic
1.4 electrical propenies
1.5 summary
1.6 funher reading
exercises
2 combinational logic design
2.1 boolean algebra
2.2 logic gates
2.3 combinational logic design
2.4 timing
2.5 number codes
2.6 summary
2.7 funher reading
exercises
3 combinational logic using vhdl gate models
3.1 entities and architectures
. 3.2 identifiers, spaces and commenb
3.3 netlists
3.4 signal assignments
3.5 generics
3.6 constant and open pons
3.7 testbenches
3.8 configurations
3.9 summary
3.10 funher reading
exercises
4 combinatlonal building blocks
4.1 three-state buffers
4.2 decoders
4.3 multiplexers
4.4 priority encoder
4.5 adders
4.6 parity checker
4.7 summary
4.8 further reading
exercises
5 synchronous sequential design
5.1 synchronous sequential systems
5.2 models of synchronous sequential systems
5.3 algorithmic state machines
5.4 synthesis from asm charts
5.5 5tate machines in vhdl
5.6 summary
5.7 funher reading
exercises
6 vhdl models of sequentlal logic blocks
6.1 latches
6.2 flip-fiops
6.3 jk and t flip-flops
6.4 registers and shift registers
6.5 counters
6.6 memory
6.7 sequential multiplier
6.8 summary
6.9 funher reading
exercises
7 complex sequential systems
7.1 linked state machines
7.2 datapath/controller panitioning
7.3 instructions
7.4 a simple microprocessor
7.5 vhdl model of a simple microprocessor
7.6 summary
7.7 futher reading
exercises
8 vhdl simulation
8.1 event-driven simulation
8.2 simulation of vhdl models
8.3 simulation modelling issues
8.4 fike operations
8.5 summary
8.6 funher reading
exercises
9 vhdl synthesls
9.1 rtl synthesis
9.2 constraints
9.3 synthesis for fpcas
9.4 behavioural synthesis
9.5 summary
9.6 futher reading
exercises
10 testing digital systems
1o.1 the need for testing
10.2 fault models
10.3 fault-oriented test pattern generation
10.t fault simulation
10.5 fault simulation in vhdl
10.6 summary
10.7 further reading
exercises
11 design for testability
11.1 ad hoc testability improvements
11.2 structured design for test
11.3 built-in self-test
11.4 boundary scan (ieee 1149.1)
11.5 summary
11.6 further reading
exercises
12 asynthronous sequential design
12.1 asynchronous circuib
12.2 analysis of asynchronous circuits
12.3 design of asynchronous sequential circuits
12.4 setup and hold times and metastability
12.5 summary
12.6 further reading
exercises
appendices
a vhdl standards
b verilog
c 1076a - shared variables
bibliography
answers to selected problems
index
